The present invention relates to a reverse voltage protection device for a logic circuit; more particularly, it applies to such a protection device for a chip comprising a logic portion and a power portion of the MOS vertical transistor type.
FIG. 1 shows an electric circuit diagram comprising a voltage source 1, for example a car battery, a power switching portion 2 and a logic portion 3. The power switching portion 2 permits to feel a loan L. The logic portion 3 is provided with external inputs 4. A zener diode, not shown in the figure, is generally connected in parallel with the voltage source. This zener diode permits clipping of the voltage when the voltage source supplies a forward current.
The protection of the logic circuit 3 against reverse voltages has to be ensured by a diode 5. This diode is placed outside of the logic portion 3. It would be very advantageous that diode 5 be part of the same integrated circuit as the logic portion 3.
FIG. 2 is a section view of an exemplary conventional dual structure wherein the power portion is schematically represented by a vertical diffused power MOS transistor (VDMOS) TP and the logic portion by a lateral MOS transistor TL.
The structure is realized in a substrate 11 of a first conductivity type, for example of the N-type. A cell of the power MOS transistor TP comprises a region 9-1, 9-2 constituted by diffusions of a second conductivity type, for example of the P-type. In each region 9-1, 9-2, are realized two N.sup.+ -type diffusions 14 which constitute the power transistor source. The two diffusions 14 are interconnected by a conductive layer 15 which is for example made of aluminum. The lateral edges of regions 9-1, 9-2 constitute a channel region 20 of the power transistor.
Each cell of the power MOS transistor TP comprises a gate 12 formed by a polycrystalline silicon layer. This gate 12 is separated from substrate 11 by an oxide layer 13.
The rear surface 17 of substrate 11 comprises an overdoped layer 19 coated with a drain metallization 18.
The MOS transistor TL of the logic portion is formed in a P-type well 24. This well 24 comprises two N.sup.+ - type diffusions, the first diffusion constituting the source 22 and the second diffusion constituting the drain 23 of transistor TL. This transistor comprises a gate 21 constituted by a polycrystalline silicon layer. Gate 21 is separated from well 24 by an oxide layer 25. Each diffusion constituting the source 22 and the drain 23 is connected to a conductive line referenced 26, 27, respectively. Those conductive lines 26, 27 are for example made of aluminum.
Conventionally, there is provided in well 24 a P.sup.+ -type area 28 connected to a conductive layer 29. Area 28 and the conductive layer 29 permit to ground well 24.
In order to realize an integrated protection diode for the logic circuit in a structure of the type shown in FIG. 2, the solution illustrated in FIG. 3 could be envisaged.
FIG. 3 shows the logic transistor TL formed in a well 24 which comprises a diffusion constituting the source 22 and a diffusion constituting the drain 23 of the transistor. The transistor also includes a gate 21.
In this structure, the P.sup.+ area 28 shown in FIGl. 2, is replaced by an N.sup.+ - type area 41. This structure thus exhibits a diode 42 at the junction between the P-type well 24 and area 41.
This diode 42 ensures the protection of the logic portion 3 against reverse voltages. However, this configuration presents several drawbacks.
First, the ground level is shifted by a voltage corresponding to the voltage drop across the terminals of a forward biased diode. This voltage drop V.sub.F has a typical value of 0.7 volt. For example, in case of a TTL-type logic having two states "0" and "1", the logic level "0" corresponds to a voltage lower than 0.4 volt and the logic level "1" corresponds to a voltage higher than 2 volts. With a 0.7 volt difference, level "0" corresponding to the configuration shown in FIG. 3 will not be compatible with level "0"of the TTL logic.
A second drawback is due to the fact that diode 42 is in fact realized by the emitter-base junction of an NPN parasitic bipolar transistor, the collector of which is constituted by the N-type layers 11, 19, the emitter is constituted by area 41 and the base is constituted by well 24, the base not being connected to a defined voltage.
This NPN parasitic bipolar transistor with a floating base exhibits a poor breakdown voltage (a breakdown voltage lower than that of the power MOS transistor TP). Thus, when the power MOS transistor is at the blocked state, the occurence of a high voltage across the terminals of the voltage source will cause the breakdown of the NPN parasitic bipolar transistor before that of the power MOS transistor TP.